1. Field of the Invention
The present invention relates to a technology for analyzing signal levels of components of an electronic circuit.
2. Description of the Related Art
FIG. 9 is a schematic for explaining an example of a conventional method of verifying a design of an electronic circuit. The verification method is one of simple methods in which a simulation model 103 is created of a circuit that is to be verified. The simulation model 103 alone is incapable of verification, and therefore, a test bench 104 is created to input a test pattern 102 thereto. Then, the simulation model 103 is incorporated into the test bench 104. The test pattern 102 is added to the simulation model 103, and simulation is performed. A plurality of simulators that performs the simulation has a function of recording the signal level of wiring in the simulation model during the simulation, which enables to acquire waveform information 101 at the time of the simulation. The waveform information 101 records signal-level values at respective time points of the simulation. Although the waveform information 101 is acquired through the simulation in the above description, it is possible to acquire the waveform information 101 from actual equipment by using an analyzer such as a logic analyzer. A designer debugs by displaying as signal waveform the waveform information 101 acquired during the simulation or through the analyzer on a display device.
FIG. 10 is a schematic for explaining another example of a conventional method of verifying a design of an electronic circuit. The verification method is more efficient than the verification method illustrated in FIG. 9. As shown in FIG. 10, a result-dump unit 203 is incorporated in a test bench 204. When simulation is performed after a test pattern 202 is added to the test bench 204, the result-dump unit 203 extracts necessary information from information acquired during the simulation and outputs a dump result 205. A result-dump step 201 is incorporated in the test pattern 202 as required so that the result-dump unit 203 can function. The dump result 205 and a predetermined expected value 206 are compared in a comparing unit 207 to check whether the simulation model 103 operates as expected. This eliminates the need to display a signal to be observed as waveform and check the waveform visually, and enables more efficient verification. The simulation model 103, which is the object of verification, is the same as that shown in FIG. 9.
Japanese Patent Application Laid-Open No. H6-58968 discloses a method in which an expected value is prepared for waveform information, so that acquired waveform information is compared with the expected value according to comparison rules. The display method is changed depending on whether the waveform information and the expected value match. Thus, a difference in waveforms can be easily recognized.
Japanese Patent Application Laid-Open No. H5-266121 discloses a method in which waveform information and the expected value of the waveform information are compared and only dissimilar parts are displayed. Accordingly, it can be checked whether the waveform information and the expected value match in a short period of time.
Japanese Patent Application Laid-Open No. H9-16652 discloses a method in which an expected value of a simulation result is generated by a computer program for use in comparison.
However, according to the conventional method shown in FIG. 9, the acquired waveform information is checked visually, which affects work efficiency, and may cause human error of overlooking a mistake.
According to the conventional method shown in FIG. 10, the result-dump unit needs to be incorporated in the test bench, and sometime, the result-dump step needs to be incorporated in the test pattern. If the information to be checked is found at a later stage, simulation is performed again after addition of the result-dump unit and the result-dump step. Generally, simulation requires considerable amount of time, and if the simulation is performed again, development schedule is extended.
According to the conventional methods disclosed in Japanese Patent Application Laid-Open Nos. H6-58968 and H5-266121, the expected value is necessary for the entire simulation time of a signal that is to be verified. Consequently, considerable time is required to prepare the expected value. Further, there is a time period in which the waveform information has no effect on demand function, and naturally, there is no need to verify operation during the time period. It is difficult to identify the time period to create the expected value. According to the conventional method disclosed in Japanese Patent Application Laid-Open No. H9-16652, the expected value is created by a computer program. However, as in the above conventional methods, it is problematic to create the expected value during the time period.